A3PN015-QNG68 Datasheet, PDF (109/114 Pages) Microsemi Corporation – ProASIC3 nano Flash FPGAs

Revision
Revision 8
(continued)
ProASIC3 nano Flash FPGAs
Changes
Page
The following tables were updated with available information:
Table 2-8 · Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software
Settings; Table 2-9 · Summary of I/O Output Buffer Power (per pin) – Default I/O
Software Settings1; Table 2-10 • Different Components Contributing to Dynamic
Power Consumption in ProASIC3 nano Devices; Table 2-14 • Summary of Maximum
and Minimum DC Input and Output Levels; Table 2-18 • Summary of I/O Timing
Characteristics—Software Default Settings (at 35 pF); Table 2-19 • Summary of I/O
Timing Characteristics—Software Default Settings (at 10 pF)
2-6
through
2-18
Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances was revised to add wide range 2-19
data and correct the formulas in the table notes (SAR 21348).
The text introducing Table 2-24 • Duration of Short Circuit Event before Failure was
revised to state six months at 100° instead of three months at 110° for reliability
concerns. The row for 110° was removed from the table.
2-20
Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability was revised to
give values with Schmitt trigger disabled and enabled (SAR 24634). The temperature
for reliability was changed to 100ºC.
2-21
Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS
Wide Range and the timing tables in the "Single-Ended I/O Characteristics" section
were updated with available information. The timing tables for 3.3 V LVCMOS wide
range are new.
2-22
The following sentence was deleted from the "2.5 V LVCMOS" section: "It uses a 5 V– 2-30
tolerant input buffer and push-pull output buffer."
Values for t_DDRISUD and F_DDRIMAX were updated in Table 2-62 • Input DDR
Propagation Delays. Values for F_DDOMAX were added to Table 2-64 • Output DDR
Propagation Delays (SAR 23919).
2-46,
2-48
Table 2-67 • A3PN010 Global Resource through Table 2-70 • A3PN060 Global 2-54
Resource were updated with available information.
through
2-55
Table 2-73 • ProASIC3 nano CCC/PLL Specification was revised (SAR 79390).
2-57
Revision 11
5-3