VCT38XXA Datasheet, PDF (92/172 Pages) Micronas – Video/Controller/Teletext IC Family

VCT 38xxA
ADVANCE INFORMATION
Bandgap
CPU Reset
V_REFPOR
VSUP_S
V_REFA
V_REFR
V_REFPOR
RESET
Interrupt
>1
Source
internal Reset to DMA, TPU, VDP
RC.VSI ^Voltage
Supervision
RC.TPUI ^TPU
Watchdog
RC.ALI
VSUP_D
V_REFA
>1 _RC.RESDIS
Watchdog
>1
+
-
>1
&
Clock
Supervision
CSW0.CSA
RC.RESOUT
>1
SQ
R
V_REFR
RESQ
RC
Reset
Control
Reset extension
&
16 or 4096
oscillator pulses
>1 ^reset
Fig. 5–3: Block diagram of reset logic
5.7.3.1. Supply Supervision
An internal bandgap reference voltage is compared to
VSUP_S. A VSUP_S level below the Supply Supervision
threshold VREFPOR will permanently pull the pin
RESQ low and thus hold the VCT 38xxA in reset state
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
5.7.3.2. Clock Supervision
The Clock Supervision monitors the CPU clock fre-
quency f_CPU. A frequency level below the clock super-
vision threshold of approx. 200 kHz will permanently
pull the pin RESQ low and thus hold the IC in reset
(see Fig. 5–3 on page 92). This reset source is active
after reset and can be enabled/disabled by flag CSA in
register CSW0.
A frequency exceeding the specified clock frequency is
not detected.
92
Micronas