VCT38XXA Datasheet, PDF (33/172 Pages) Micronas – Video/Controller/Teletext IC Family

ADVANCE INFORMATION
VCT 38xxA
Table 2–3: I²C control and status registers of the video front-end
I²C Sub Number Mode
address of bits
h’35
8
r
h’36
16
w
h’37
16
w
h’38
16
w/r
h’12
16
r
h’29
16
w/r
h’22
16
w/r
Function
FP Interface
FP status
bit [0]
bit [1]
bit [2]
write request
read request
busy
bit[8:0]
bit[11:9]
9-bit FP read address
reserved, set to zero
bit[8:0]
bit[11:9]
9-bit FP write address
reserved, set to zero
bit[11:0]
FP data register, reading/writing to this
register will autoincrement the FP read/
write address. Only 16 bit of data are
transferred per I²C telegram.
Black Line Detector
read only register, do not write to this register!
after reading, LOWLIN and UPLIN are reset to 127 to start a
new measurement
bit[6:0]
number of lower black lines
bit[7]
always 0
bit[14:8]
number of upper black lines
bit[15]
normal/black picture
Miscellaneous
Test pattern generator:
bit[10:0]
reserved (set to 0)
bit[11] 0/1
disable/enable test pattern generator
bit[13:12]
output mode:
00
Y/C = ramp (240 ... 17)
01
Y/C = 16
10
Y/C = 90
11
Y/C = 240
bit[15:14] 0/1
reserved (set to 0)
NEWLINE (available for versions with panorama scaler only):
bit[10:0]
NEWLINE register
This register defines the readout start of
the next line in respect to the value of the
sync counter.
bit [15:11]
reserved (set to 0)
Default Name
FPSTA
FPRD
FPWR
FPDAT
BLKLIN
LOWLIN
UPLIN
BLKPIC
TPG
0
0 TPGEN
0 TPGMODE
0
NEWLIN
0
Micronas
33