MSP3410B Datasheet, PDF (64/68 Pages) Micronas – Multistandard Sound Processor

MSP 3410 B
PRELIMINARY DATA SHEET
20. APPENDIX C: Documentation of known hardware restrictions for TC≤ 15
I²C-Bus
The I²C-Clock line must not be clocked in between two data transmissions (from last stop condition to next start condi-
tion). This may occur in multi bus I²C-systems with shared clock line (s. Figure 1), if protocol 1 is applied. As a prelimi-
nary workaround we recommend using protocol 2.
Figure 1
MSP 3410 B
other I²C
Devices
Data1
Data2
I²C_CL I²C_Data1 I²C_Data2
µC
Protocol 1
not working!
I²C_CL
I²C_D1
I²C_D2
Protocol 2
suggested
workaround
I²C_CL
I²C_D1
I²C_D2
Start
MSP-DATA Stop
Start
other data Stop
Start
MSP-DATA Stop
Start
Stop
MSP-Pseudo-Data
Start
other data Stop
No problem was found in multi bus I²C-systems with shared data line and multiple clock lines (s. Figure 2):
Figure 2
MSP 3410 B
other I²C
Devices
Clock1
Clock2
I²C_Data I²C_CL1 I²C_CL2
µC
I²C_D
I²C_C1
I²C_C2
Start
MSP-DATA Stop
Start
other data Stop
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