MSP3410B Datasheet, PDF (38/68 Pages) Micronas – Multistandard Sound Processor

MSP 3410 B
PRELIMINARY DATA SHEET
13.3. Pin Configurations
S_ID
NC
S_DA_IN
I2S_DA_IN
I2S_DA_OUT
I2S_WS
I2S_CL
I2C_DA
I2C_CL
S_CL
DVSUP
DVSS
S_DA_OUT
FRAME
N_CL
N_DA
RESETQ
D_CTR_IN
STANDBYQ
ADR_SEL
D_CTR_OUT0
D_CTR_OUT1
CW_DA
CW_CL
NC
AUD_CL_OUT
DMA_SYNC
XTAL_OUT
XTAL_IN
TESTIO1
ANA_IN2+
ANA_IN–
ANA_IN1+
AVSUP
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
MSP 3410 B
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DACA_R
DACA_L
VREF2
DACM_R
DACM_L
TESTIO2
C_DACS_R
C_DACS_L
ASG3
SC2_OUT_R
SC2_OUT_L
VREF1
SC1_OUT_R
SC1_OUT_L
CAPL_A
AHVSUP
CAPL_M
AVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
AHVSS
AGNDC
PDMC1
PDMC2
BAGNDI
NC
SC3_IN_L
SC3_IN_R
ASG2
Fig. 13–3: 68-pin PLCC package
AUD_CL_OUT 1
CW_CL 2
CW_DA 3
D_CTR_OUT1 4
D_CTR_OUT0 5
ADR_SEL 6
STANDBYQ 7
D_CTR_IN 8
I2C_CL 9
I2C_DA 10
I2S_CL 11
I2S_WS 12
I2S_DA_OUT 13
I2S_DA_IN 14
S_DA_IN 15
S_ID 16
S_CL 17
DVSUP 18
DVSS 19
S_DA_OUT 20
FRAME 21
N_CL 22
N_DA 23
RESETQ 24
DACA_R 25
DACA_L 26
VREF2 27
DACM_R 28
DACM_L 29
TESTIO2 30
C_DACS_R 31
C_DACS_L 32
64 DMA_SYNC
63 XTAL_OUT
62 XTAL_IN
61 TESTIO1
60 ANA_IN2+
59 ANA_IN–
58 ANA_IN1+
57 AVSUP
56 AVSS
55 MONO_IN
54 VREFTOP
53 SC1_IN_R
52 SC1_IN_L
51 ASG1
50 _{SC2_IN_R}
49 _{SC2_IN_L}
48 ASG2
47 SC3_IN_R
46 SC3_IN_L
45 BAGNDI
44 PDMC2
43 PDMC1
42 AGNDC
41 AHVSS
40 CAPL_M
39 AHVSUP
38 CAPL_A
37 SC1_OUT_L
36 SC1_OUT_R
35 VREF1
34 SC2_OUT_L
33 SC2_OUT_R
Fig. 13–4: 64-pin PSDIP package
38
ITT Semiconductors