MSP3410B Datasheet, PDF (20/68 Pages) Micronas – Multistandard Sound Processor

MSP 3410 B
PRELIMINARY DATA SHEET
Bit
Function
MODE_REG 0083_hex
Comment
Definition
[7]
FM1 FM2
MSP-channel 1 mode
0 = Nicam
1 = FM
[8]
FM AM
MSP-channel 1/2 mode
0 = FM
1 = AM
[9]
HDEV
High Deviation Mode
(channel matrix must be
sound A)
0 = normal
1 = high deviation mode
[10]
S-Bus Setting
configuration of internal
sound bus
0 = Nicam/FM-Mono
1 = Two Carrier FM
[11]
S-Bus Mode²⁾
mode of sound bus³⁾
0 = Tristate
1 = Active
[15:12] reserved
reserved
must be 0
1) _{In case of NICAM operation, I}2_{S-slave mode or synchronization to DMA not possible.}
In case of synchonization to DMA, no I²S-slave mode or NICAM is allowed.
In case of I²S-slave mode, no synchonization to DMA or NICAM is allowed.
2) _{The normal operation mode is ‘Active’}
3) _{To reduce radiation, the pins S_DA_OUT, S_CL, and S_ID should be switched to tristate if not}
used. IF S-Bus Mode = ‘tristate’, pins ‘Frame’, N_CL, and N_DA are also switched to tristate.
Recom-
mendation
X
0
0
X
0
0
X: Depend-
ing on mode
11.2.3. FIR-Parameter
The following data values (see Table 11–6) are to be
transferred 8 bits at a time embedded LSB-bound in
a 16 bit word. Note: These sequences must be obeyed.
To change a coefficient set, the complete block
FIR_REG_1 or FIR_REG_2 must be transmitted. The
new coefficient set will be active without a load_reg rou-
tine.
Table 11–6: Loading sequence for FIR-coefficients
FIR_REG_1 0001_hex (Channel 1: NICAM/FM2)
No. Symbol Name
Bits Value
1
NICAM/FM2_Coeff. (5) 8
2
NICAM/FM2_Coeff. (4) 8
see Table 11–7.
3
NICAM/FM2_Coeff. (3) 8
4
NICAM/FM2_Coeff. (2) 8
5
NICAM/FM2_Coeff. (1) 8
6
NICAM/FM2_Coeff. (0) 8
20
FIR_REG_2 0005_hex (Channel 2: FM1/FM mono)
No. Symbol Name
Bits Value
1
* IMREG1 (8 LSBS)
8
04 HEX
2
* IMREG1 / IMREG2
8
(4 MSBs / 4 LSBs)
40 HEX
3
* IMREG2 (8 MSBs)
8
00 HEX
4
FM_Coef (5)
8
see Table
11–7.
5
FM_Coef (4)
8
6
FM_Coef (3)
8
7
FM_Coef (2)
8
8
FM_Coef (1)
8
9
FM_Coef (0)
8
* IMREG_1/2: Two 12-bit off-set constants
IMREG1 and IMREG2 are used to compensate for DC-
offset, which are inherent to the FIR filter structure. IM-
REG1 is valid for the FIR_REG_1, IMREG2 for
FIR_REG_2. In the Table above, IMREG1= IMREG2 =
004. Due to the partitioning to 8 bit units, the values
04hex, 40hex, and 00hex arise.
ITT Semiconductors