MSP3410B Datasheet, PDF (59/68 Pages) Micronas – Multistandard Sound Processor

PRELIMINARY DATA SHEET
MSP 3410 B
MSP Clock Output
Clock Inverter Output
typ. 20 ns
at inverter output
Timing window
for the low to high edge at
pin 17 of DMA 2381 (XTAL2)
< 42 ns
> 10 ns
Fig. 16–2: Timing requirements for the clock signal at the DMA 2381 clock input
In the following table, the input/output clock-specification of the D2MAC circuit is shown.
Table 16–1: Clock input and output specification for MSPs
XTAL_IN min
(minimum amplitude)
C input
(after Reset)
AUD_CL_OUT min
with C load
Rout (HF) typ.
MSP 3400 C –C6
new Version
> 0.7 Vpp
22 pF
> 1.2 Vpp
40 pF
150 Ω
MSP 3410/00B –F7
new Version
> 0.7 Vpp
22 pF
> 1.2 Vpp
40 pF
120 Ω
MSP 3410/00B TC15
actual Version
> 0.7 Vpp
31 pF
> 1.0 Vpp
43 pF
120 Ω
Table 16–2: Clock input and output specification for ICs connected to MSP
XTAL_IN min
Clock-in min
(minimal amplitude)
C input
DMA 2381
> 0.7 Vpp
24 pF
10 pF with: Adr.
204,14=1
DMA 2386
> 0.7 Vpp
7pF
For the DMA_SYNC input specification of the MSP,
please refer to page 42 “V_DMAIL, V_DMAIH.”
AMU2481
> 0.7 Vpp
7pF
ITT Semiconductors
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