PC28F256P30BFA Datasheet, PDF (91/98 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

AC Write Specifications
256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Write Specifications
Table 45: AC Write Specifications
Parameter
Symbol
RST# HIGH recovery to WE# LOW
t_PHWL
CE# setup to WE# LOW
t_ELWL
WE# write pulse width LOW
t_WLWH
Data setup to WE# HIGH
t_DVWH
Address setup to WE# HIGH
t_AVWH
CE# hold from WE# HIGH
t_WHEH
Data hold from WE# HIGH
t_WHDX
Address hold from WE# HIGH
t_WHAX
WE# pulse width HIGH
t_WHWL
V_PP setup to WE# HIGH
V_PP hold from status read
WP# hold from status read
t_VPWH
t_QVVL
t_QVBL
WP# setup to WE# HIGH
t_BHWH
WE# HIGH to OE# LOW
t_WHGL
WE# HIGH to read valid
t_WHQV
Write to Asynchronous Read Specifications
WE# HIGH to address valid
t_WHAV
Write to Synchronous Read Specifications
WE# HIGH to clock valid
t_WHCH/L
WE# HIGH to ADV# HIGH
t_WHVH
WE# HIGH to ADV# LOW
t_WHVL
Write Specification with Clock Active
ADV# HIGH to WE# LOW
t_VHWL
Clock HIGH to WE# LOW
t_CHWL
Min
150
0
50
50
50
0
0
0
20
200
0
0
200
0
t_AVQV + 35
0
19
19
7
-
-
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 12
1, 2
1, 2, 5
1, 2, 3, 7
1, 2, 3, 7
1, 2, 9
1, 2, 3, 6, 10
ns
1, 2, 3, 6, 8
ns
1, 2, 3, 6, 10
ns
ns
ns
1, 2, 3, 11
ns
Notes:
1. Write timing characteristics during erase suspend are the same as WRITE-only opera-
tions.
2. A WRITE operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width LOW (^tWLWH or ^tELEH) is defined from CE# or WE# LOW (whichever
occurs last) to CE# or WE# HIGH (whichever occurs first). Thus, ^tWLWH = ^tELEH = ^tWLEH
= ^tELWH.
5. Write pulse width HIGH ^tWHWL or ^tEHEL) is defined from CE# or WE# HIGH whichever
occurs first) to CE# or WE# LOW whichever occurs last). Thus, ^tWHWL = ^tEHEL = t_WHEL =
t_EHWL).
6. ^tWHVH or ^tWHCH/L must be met when transitioning from a WRITE cycle to a synchro-
nous BURST read.
7. V_PP and WP# should be at a valid level until erase or program success is determined.
8. This specification is only applicable when transitioning from a WRITE cycle to an asyn-
chronous read. See spec ^tWHCH/L and ^tWHVH for synchronous read.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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