PC28F256P30BFA Datasheet, PDF (49/98 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

256Mb and 512Mb (256Mb/256Mb), P30-65nm
Configuration Register
Table 18: End of Wordline Data and WAIT State Comparison
Latency Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
130nm
Data Words
WAIT States
Not Supported
Not Supported
4
0 to 1
4
0 to 2
4
0 to 3
4
0 to 4
4
0 to 5
4
0 to 6
Not Supported
Not Supported
65nm
Data Words
WAIT States
Not Supported
Not Supported
16
0 to 1
16
0 to 2
16
0 to 3
16
0 to 4
16
0 to 5
16
0 to 6
16
0 to 7
16
0 to 8
16
0 to 9
16
0 to 10
16
0 to 11
16
0 to 12
16
0 to 13
16
0 to 14
WAIT Signal Polarity and Functionality
The WAIT polarity (WP) bit, RCR10 determines the asserted level (V_OH or V_OL) of WAIT.
When WP is set, WAIT is asserted HIGH (default). When WP is cleared, WAIT is asserted
LOW. The WAIT signal changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# de-asserted).
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR15 = 0). The WAIT signal is only de-asserted when data is valid on the bus. When
the device is operating in synchronous nonarray read mode, such as read status, read
ID, or read CFI, the WAIT signal is also de-asserted when data is valid on the bus. WAIT
behavior during synchronous nonarray reads at the end of wordline works correctly on-
ly on the first data access. When the device is operating in asynchronous page mode,
asynchronous single word read mode, and all write operations, WAIT is set to a de-as-
serted state as determined by RCR10.
Table 19: WAIT Functionality Table
Condition
CE# = 1, OE# = X or CE# = 0, OE# = 1
CE# = 0, OE# = 0
Synchronous Array Reads
Synchronous Nonarray Reads
All Asynchronous Reads
WAIT
High-Z
Active
Active
Active
De-asserted
Notes
1
1
1
1
1
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p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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