PC28F256P30BFA Datasheet, PDF (78/98 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

256Mb and 512Mb (256Mb/256Mb), P30-65nm
Power and Reset Specifications
Figure 26: Reset Operation Waveforms
(A) Reset during
read mode
RST# ^VIH
V_IL
(B) Reset during
program or block erase
P1 ≤ P2
RST# ^VIH
V_IL
(C) Reset during
program or block erase
P1 ≥ P2
RST# ^VIH
V_IL
(D) V_CC power-up to
RST# HIGH
V_CC
V_CC
0V
t_PLPH
t_PHQV
t_PLRH
Abort
complete
t_{PLRH Abort}
complete
t_VCCPH
t_PHQV
t_PHQV
Power Supply Decoupling
The device requires careful power supply de-coupling. Three basic power supply cur-
rent considerations are 1) standby current levels, 2) active current levels, and 3) transi-
ent peaks produced when CE# and OE# are asserted and de-asserted.
When the device is accessed, internal conditions change. Circuits within the device ena-
ble charge pumps, and internal logic states change at high speed. These internal activi-
ties produce transient signals. Transient current magnitudes depend on the device out-
puts’ capacitive and inductive loading. Two-line control and correct de-coupling capac-
itor selection suppress transient voltage peaks.
Because the devices draw their power from V_CC, V_PP, and V_CCQ, each power connection
should have a 0.1µF and a 0.01µF ceramic capacitor to ground. High-frequency, inher-
ently low-inductance capacitors should be placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
78
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