MT28F160A3 Datasheet, PDF (9/28 Pages) Micron Technology – FLASH MEMORY

ADVANCE
1 MEG x 16
ENHANCED BOOT BLOCK FLASH MEMORY
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored by
toggling OE# and CE# and by reading the resulting status
code on I/Os DQ0-DQ7. The high-order I/Os (DQ8-DQ15)
are set to 00h internally, so only the low-order I/Os (DQ0-
DQ7) need interpreting.
Register data is updated on the falling edge of OE# or
CE#. The latest falling edge of either of these two signals
updates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register monitoring. To ensure
that the status register output contains updated status
data, CE# or OE# must be toggled for each subsequent
STATUS READ.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 4 defines the status
register bits.
After monitoring the status register during a PRO-
GRAM/ERASE, the data appearing on DQ0-DQ7 remains
as status register data until a new command is issued to
the CSM. To return the device to other modes of opera-
tion, a new command must be issued to the CSM.
COMMAND STATE MACHINE
OPERATIONS
The CSM decodes instructions for read, read device
identification code, read status register, clear status reg-
ister, program, erase, erase suspend, erase resume, pro-
gram suspend, and program resume. The 8-bit com-
mand code is input to the device on DQ0-DQ7 (see Table
2 for CSM codes). During a PROGRAM or ERASE cycle,
the CSM informs the WSM that a PROGRAM or ERASE
cycle has been requested.
During a PROGRAM cycle, the WSM controls the pro-
gram sequences and the CSM responds to a PROGRAM
SUSPEND command only. During an ERASE cycle, the
CSM responds to an ERASE SUSPEND command only.
When the WSM has completed its task, the WSM status
bit (SR7) is set to a logic HIGH level and the CSM responds
to the full command set. The CSM stays in the current
command state until the microprocessor issues another
command.
The WSM successfully initiates an ERASE or PRO-
GRAM operation only when VPP is within its correct volt-
age range. For data protection, it is required that RP# be
held at a logic LOW level during a CPU reset.
CLEAR STATUS REGISTER
The WSM can set to “1” the block lock status bit (SR1),
the VPP status bit (SR3), the program status bit (SR4), and
the erase status bit (SR5) of the status register. The CLEAR
STATUS REGISTER command (50h) allows the external
microprocessor to clear these status bits and synchro-
nize to internal operations. After issuing this command,
the status bits are cleared and the device returns to the
read array mode.
READ OPERATIONS
Three READ operations are available: read array, read
device identification code, and read status register.
READ ARRAY
The array is read by entering the command code FFh
on DQ0-DQ7. Control signals CE# and OE# must be at a
logic LOW level (VIL) and WE# and RP# must be at a logic
HIGH level (VIH) to read data from the array. Data is
available on DQ0-DQ15. Any valid address within any of
the blocks selects that address and allows data to be read
from that address. Upon initial power-up, the device
defaults to the read array mode.
READ DEVICE IDENTIFICATION CODE
Device identification codes are read by entering com-
mand code 90h on DQ0-DQ7. Two bus cycles are re-
quired for this operation, the first to enter the command
code and the second to read the selected code. Control
signals CE# and OE# must be at a logic LOW level (VIL)
and WE# and RP# must be at a logic HIGH level (VIH). The
manufacturer code is obtained on DQ0-DQ15 in the sec-
ond cycle, after the identify address 00000h is latched.
The device code is obtained on DQ0-DQ15 in the second
cycle, after the identify address 00001h is latched (see
Table 3).
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0-DQ7. Control signals CE# and OE#
must be at a logic LOW level (VIL), and WE# and RP# must
be at a logic HIGH level (VIH). Two bus cycles are required
for this operation: one to enter the command code, and
one to read the status register. The status register con-
tents are updated on the falling edge of CE# or OE#,
whichever occurs last within the cycle.
1 Meg x 16 Enhanced Boot Block Flash Memory
MT28F160A3_3.p65 – Rev. 3, Pub. 8/01
9
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©2001, Micron Technology, Inc.