MT28F160A3 Datasheet, PDF (14/28 Pages) Micron Technology – FLASH MEMORY

ADVANCE
1 MEG x 16
ENHANCED BOOT BLOCK FLASH MEMORY
Figure 4
Automated BLOCK ERASE Flowchart
Start
Issue ERASE SETUP
Command
Issue Block Address
and ERASE
CONFIRM Command
Read Status Register
Bits
NO
SR7 = 1?
YES
Full Status Register
Check (optional)¹
ERASE
SUSPEND Loop
NO
ERASE
SUSPEND?
YES
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
ERASE
SETUP
Data = 20h
Addr = Don’t Care
WRITE
ERASE
Data = D0h
Block Addr = Address
within block to be erased
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to reset the
device to read array mode.
BLOCK ERASE
Completed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
SR1 = 0?
YES
NO _{ERASE Attempted}
on a Locked Block
SR3 = 0?
NO
VPP Range Error
YES
SR4 = 1 and
SR5 = 1?
NO
YES _{Command Sequence}
Error
SR5 = 0?
NO
BLOCK ERASE Failed
YES
BLOCK ERASE Passed
BUS
OPERATION
Standby
Standby
Standby
Standby
COMMAND
COMMENTS
Check SR1
1 = Detect locked block
Check SR3²
1 = Detect VPP low
Check SR4 and SR5
1 = BLOCK ERASE command
error
Check SR5³
1 = BLOCK ERASE error
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
1 Meg x 16 Enhanced Boot Block Flash Memory
MT28F160A3_3.p65 – Rev. 3, Pub. 8/01
14
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©2001, Micron Technology, Inc.