MT47H32M16HR-25E Datasheet, PDF (89/132 Pages) Micron Technology – DDR2 SDRAM

ACTIVATE
512Mb: x4, x8, x16 DDR2 SDRAM
ACTIVATE
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVATE command, which selects both the bank
and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row subject to the ^tRCD specification. ^tRCD (MIN) should be divided
by the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a ^tRCD (MIN) specification of 20ns with a 266 MHz
clock (^tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 42,
which covers any case where 5 < ^tRCD (MIN)/^tCK ≤ 6. Figure 42 also shows the case for
t_{RRD where 2 <} t_{RRD (MIN)/}t_{CK ≤ 3.}
Figure 42: Example: Meeting ^tRRD (MIN) and ^tRCD (MIN)
CK#
T0
CK
Command
ACT
Address
Row
Bank address
Bank x
T1
T2
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Row
Row
Col
tRRD
Bank y
tRRD
tRCD
Bank z
Bank y
Don’t Care
A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by ^tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is
defined by ^tRRD.
DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: ^tFAW. This
requires no more than four ACTIVATE commands may be issued in any given ^tFAW
(MIN) period, as shown in Figure 43 (page 90).
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
89
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