MT47H32M16HR-25E Datasheet, PDF (29/132 Pages) Micron Technology – DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – I_DD Parameters
Table 11: DDR2 I_DD Specifications and Conditions (Die Revision G) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition
Configura-
-25E/
Symbol
tion
-187E -25 -3E/-3 -37E -5E
Operating burst write current: All
banks open, continuous burst writes;
BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK
(I_DD), ^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP
(I_DD); CKE is HIGH, CS# is HIGH be-
tween valid commands; address bus
inputs are switching; Data bus inputs
are switching
I_DD4W
x4, x8
x16
TBD
125
115
99
85
TBD
160
135
120
105
Operating burst read current: All
banks open, continuous burst reads,
I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL =
0; ^tCK = ^tCK (I_DD),
t_{RAS =} t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD);}
CKE is HIGH, CS# is HIGH between val-
id commands; address bus inputs are
switching; Data bus inputs are switch-
ing
I_DD4R
x4, x8
x16
TBD
120
110
95
80
TBD
150
125
110
95
Burst refresh current: ^tCK = ^tCK
I_DD5
(I_DD); refresh command at every ^tRFC
(I_DD) interval; CKE is HIGH, CS# is
HIGH between valid commands; Oth-
er control and address bus inputs are
switching; Data bus inputs are switch-
ing
x4, x8
x16
TBD
95
90
90
87
TBD
100
90
90
87
Self refresh current: CK and CK# at I_DD6
x4, x8, x16
TBD
7
0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data
I_DD6L
TBD
3
bus inputs are floating
7
7
7
3
3
3
Operating bank interleave read
I_DD7
current: All bank interleaving reads,
I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL =
t_{RCD (IDD) - 1 x} t_{CK (IDD);} t_{CK =} t_CK
(I_DD), ^tRC = ^tRC (I_DD), ^tRRD = ^tRRD
(I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH,
CS# is HIGH between valid commands;
address bus inputs are stable during
deselects; Data bus inputs are switch-
ing; See I_DD7 Conditions (page 24) for
details
x4, x8
x16
TBD
150
140
135
130
TBD
215
200
195
190
Units
mA
mA
mA
mA
mA
Notes:
1. I_DD specifications are tested after the device is properly initialized. 0°C ≤ T_C ≤ +85°C.
2. V_DD = +1.8V ±0.1V, V_DDQ = +1.8V ±0.1V, V_DDL = +1.8V ±0.1V, V_REF = V_DDQ/2.
3. I_DD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. I_DD values must be met with all combinations of EMR bits 10 and 11.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
29
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