MT47H32M16HR-25E Datasheet, PDF (70/132 Pages) Micron Technology – DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Commands
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
MODE command selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 47
(page 95) and Figure 59 (page 106) for other restrictions and details.
9. The power-down mode does not perform any REFRESH operations. The duration of power-
down is limited by the refresh requirements outlined in the AC parametric section.
Table 38: Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table
Current
State
CS# RAS# CAS#
Any
H
X
X
L
H
H
Idle
L
L
H
L
L
L
L
L
L
Row active
L
H
L
L
H
L
L
L
H
Read (auto
L
H
L
precharge
L
H
L
disabled)
L
L
H
Write
L
H
L
(auto pre-
L
H
L
charge disa-
bled)
L
L
H
WE#
X
H
H
H
L
H
L
L
H
L
L
H
L
L
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVATE (select and activate row)
REFRESH
LOAD MODE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (start PRECHARGE)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (start PRECHARGE)
Notes
7
7
8
8
9
8
8, 10
9
8
8
9
Notes:
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after ^tXSNR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, ^tRP has been met, and any READ burst is com-
plete.
Row A row in the bank has been activated, and ^tRCD has been met. No data bursts/
active: accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled and has not yet
terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Issue DESELECT or NOP commands, or allowable commands to the other bank, on any
clock edge occurring during these states. Allowable commands to the other bank are
determined by its current state and this table, and according to Table 39 (page 72).
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
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