MT47H32M16HR-25E Datasheet, PDF (115/132 Pages) Micron Technology – DDR2 SDRAM

Figure 67: Self Refresh
512Mb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH
CK#
CK1
CKE1
T0
T1
T2
tCH tCL
tCK1
Ta0
Ta1
Ta2
Tb0
Tc0
Td0
tCK1
tISXR2
tCKE3
tIH
Command
ODT6
Address
DQS#, DQS
DQ
DM
NOP
REF
tAOFD/tAOFPD6
NOP4
NOP4
Valid5
Valid5
tIH
Valid
Valid7
tRP8
Enter self refresh
mode (synchronous)
tCKE _(MIN)9
Exit self refresh
mode (asynchronous)
tXSNR2, 5, 10
tXSRD2, 7
Indicates a break in
time scale
Don’t Care
Notes: 1. Clock must be stable and meeting ^tCK specifications at least 1 × ^tCK after entering self
refresh mode and at least 1 × ^tCK prior to exiting self refresh mode.
2. Self refresh exit is asynchronous; however, ^tXSNR and ^tXSRD timing starts at the first ris-
ing clock edge where CKE HIGH satisfies ^tISXR.
3. CKE must stay HIGH until ^tXSRD is met; however, if self refresh is being re-entered, CKE
may go back LOW after ^tXSNR is satisfied.
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
which allows any nonREAD command.
5. ^tXSNR is required before any nonREAD command can be applied.
6. ODT must be disabled and R_TT off (^tAOFD and ^tAOFPD have been satisfied) prior to enter-
ing self refresh at state T1.
7. ^tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered, ^tCKE (MIN) must be satisfied prior to exiting self
refresh.
10. Upon exiting SELF REFRESH, ODT must remain LOW until ^tXSRD is satisfied.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
115
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