PC28F512G18FF Datasheet, PDF (84/118 Pages) Micron Technology – 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory

128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Common Flash Interface
Table 47: Device Geometry (Continued)
Hex
Offset
28h
2Ah
2Ch
2Dh
31h
35h
Length Description
2 Flash device interface code assignment: n such that n +
1 specifies the bit field that represents the device
width capabilities as described here:
bit 0: x8
bit 1: x16
bit 2: x32
bit 3: x64
bits 4–7: –
bits 8–15: –
2 n such that maximum number of bytes in write buffer
= 2ⁿ
1 Number of erase block regions (x) within the device:
x = 0 indicates no erase blocking; the device erases in
bulk
x specifies the number of device regions with one or
more contiguous, same-size erase blocks
Symmetrically blocked partitions have one blocking re-
gion
4 Erase block region 1 information:
bits 0–15 = y, y + 1 = number of identical-size erase
blocks
bits 16–31 = z, region erase block(s) size are z x 256
bytes
4 Erase block region 2 information:
bits 0–15 = y, y + 1 = number of identical-size erase
blocks
bits 16–31 = z, region erase block(s) size are z x 256
bytes
4 Reserved for future erase block region information
Note: 1. See the bit field table.
Address
28:
29:
2Ah
2Bh
2Ch
2D:
30:
31:
34:
35:
38:
Table 48: Block Region Map Information
Address
27:
28:
29:
2A:
2B:
2C:
128Mb
Bottom
Top
- -18
--
- -01
--
- -00
--
- -0A
--
- -00
--
- -01
--
256Mb
Bottom
Top
- -19
--
- -01
--
- -00
--
- -0A
--
- -00
--
- -01
--
512Mb
Bottom
Top
- -1A
--
- -01
--
- -00
--
- -0A
--
- -00
--
- -01
--
Hex
Code
- -01
- -00
ASCII Value
(DQ[7:0])
x16
- -0A
- -00
1024
(page 0 )
(page 0 )
(page 0 )
(page 0 )
1Gb
Bottom
Top
- -1B
--
- -01
--
- -00
--
- -0A
--
- -00
--
- -01
--
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
84
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