PC28F512G18FF Datasheet, PDF (67/118 Pages) Micron Technology – 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory

128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
Figure 21: Synchronous Continuous Misaligned Burst Read (Non-MUX)
Latency count
CLK
A[MAX:0]
t_AVCH t_CHAX
t_CHVL t_VLCH t_CHVH
ADV#
t_ELCH
CE#
OE#
WAIT
t_GLTX
t_GLTV
DQ[15:0]
t_CLK
t_CH
t_CL
t_CHTV
t_CHTX
t_CHTV
t_CHQV
t_CHQV
t_CHQX
Q
Q
t_CHTX
t_CHTV
End of WL
RST#
Notes:
1. WAIT shown as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
2. ADV# may be held LOW throughout the synchronous READ operation.
3. ^tAVQV, ^tELQV, and ^tVLQV apply to legacy-latching only.
4. ^tACC and ^tVLVH apply to clock-latching only.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
67
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