PC28F512G18FF Datasheet, PDF (39/118 Pages) Micron Technology – 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory

128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Program Operations
Buffered Programming
Buffered programming programs multiple words simultaneously into the memory ar-
ray. Data is first written to a programming buffer and then programmed into the array
in buffer-sized increments, significantly reducing the effective word programming time.
Optimal performance and power consumption is realized only by aligning the starting
address to buffer-sized boundaries within the array. Crossing a buffer-sized boundary
can cause the buffered programming time to double.
The BUFFERED PROGRAM operation consists of the following fixed, predefined se-
quence of bus WRITE cycles: 1) Issue the SETUP command; 2) Issue a word count; 3)
Fill the buffer with user data; and 4) Issue the CONFIRM command. Once the SETUP
command has been issued to an address, subsequent bus WRITE cycles must use ad-
dresses within the same block throughout the operation; otherwise, the operation will
abort. Bus READ cycles are allowed at any time and at any address.
Note: V_PP must be at V_PPL or V_PPH throughout the BUFFERED PROGRAM operation.
Upon programming completion, the status register indicates ready (SR7 = 1), and any
valid command may be issued. A full status register check should be performed to
check for any programming errors. If any error bits are set, the status register should be
cleared using the CLEAR STATUS REGISTER command.
A subsequent BUFFERED PROGRAM operation can be initiated by issuing another SET-
UP command and repeating the buffered programming sequence. Any errors in the sta-
tus register caused by a previous operation should first be cleared to prevent masking of
errors that may occur during a subsequent BUFFERED PROGRAM operation.
Valid commands issued to the busy partition during array programming are READ AR-
RAY, READ ID, READ CFI, READ STATUS, and PROGRAM SUSPEND.
Issuing the READ ARRAY, READ ID, or READ CFI command to a partition that is actively
programming causes subsequent reads from that partition to output invalid data. Valid
data is output only after the PROGRAM operation has completed.
Buffered Enhanced Factory Programming
Buffered enhanced factory programming (BEFP) improves programming performance
through the use of the write buffer, elevated programming voltage (V_PPH), and en-
hanced programming algorithm. User data is written into the write buffer, and then the
buffer contents are automatically written into the array in buffer-sized increments.
Internal verification during programming (inherent to MLC technology) and status reg-
ister error checking are used to determine proper completion of the PROGRAM opera-
tion. This eliminates delays incurred when switching between SINGLE-WORD PRO-
GRAM and VERIFY operations.
BEFP consists of the following three distinct phases:
1. Setup phase: V_PPH and block lock checks
2. Program/verify phase: buffered programming and verification
3. Exit phase: block error check
BEFP is supported in both control mode and object mode. The programming mode se-
lection for the entire array block is driven by the specific type of information, such as
header or object data. Header/object data is aligned on a 1KB programming region
boundary in the main array block.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
39
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