MT47H128M16RT-25EITC Datasheet, PDF (80/134 Pages) Micron Technology – DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks

2Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Write Recovery
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 36 (page 78).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 65 (page 112).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing ^tWR (in
nanoseconds) by ^tCK (in nanoseconds) and rounding up a noninteger value to the next
integer; WR (cycles) = ^tWR (ns)/^tCK (ns). Reserved states should not be used as an un-
known operation or incompatibility with future versions may result.
Power-Down Mode
Active power-down (PD) mode is defined by bit M12, as shown in Figure 36. PD mode
enables the user to determine the active power-down mode, which determines per-
formance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The ^tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is en-
abled. The ^tXARDS parameter is used for slow-exit active PD exit timing. The DLL can
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I_DD3P normal and I_DD3P low-
power mode is defined in the DDR2 I_DD Specifications and Conditions table.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
80
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