MT47H128M16RT-25EITC Datasheet, PDF (43/134 Pages) Micron Technology – DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks

45. The half-clock of ^tAOFD’s 2.5 ^tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the
amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, ^tAOFD would actually be 2.5 -
0.03, or 2.47, for ^tAOF (MIN) and 2.5 + 0.03, or 2.53, for ^tAOF (MAX).
46. ODT turn-on time ^tAON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-
on time ^tAON (MAX) is when the ODT resistance is fully on. Both are measured from ^tAOND.
47. ODT turn-off time ^tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time ^tAOF (MAX)
is when the bus is in High-Z. Both are measured from ^tAOFD.
48. Half-clock output parameters must be derated by the actual ^tERR_5per and ^tJITdty when input clock jitter is present;
this will result in each parameter becoming larger. The parameter ^tAOF (MIN) is required to be derated by sub-
tracting both ^tERR_5per (MAX) and ^tJITdty (MAX). The parameter ^tAOF (MAX) is required to be derated by subtract-
ing both ^tERR_5per (MIN) and ^tJITdty (MIN).
49. The -187E maximum limit is 2 × ^tCK + ^tAC (MAX) + 1000 but it will likely be 3 x ^tCK + ^tAC (MAX) + 1000 in the
future.
50. Should use 8 ^tCK for backward compatibility.
51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-
dress may result in reduction of the product lifetime.