MT47H128M16RT-25EITC Datasheet, PDF (118/134 Pages) Micron Technology – DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks

2Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Power-Down Mode
DDR2 SDRAM supports multiple power-down modes that allow significant power sav-
ings over normal operating modes. CKE is used to enter and exit different power-down
modes. Power-down entry and exit timings are shown in Figure 70 (page 119). Detailed
power-down entry conditions are shown in Figure 71 (page 121)–Figure 78 (page 124).
Table 44 (page 120) is the CKE Truth Table.
DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and ^tWR (WRITE-to-PRECHARGE command) or ^tWTR (WRITE-to-
READ command) are satisfied, as shown in Figure 73 (page 122) and Figure 74
(page 122) on Figure 74 (page 122). The number of clock cycles required to meet ^tWTR
is either two or ^tWTR/^tCK, whichever is greater.
Power-down mode (see Figure 70 (page 119)) is entered when CKE is registered low co-
incident with an NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE op-
eration is in progress. If power-down occurs when all banks are idle, this mode is refer-
red to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deacti-
vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same volt-
age as when it entered power-down; however, the clock frequency is allowed to change
(see Precharge Power-Down Clock Frequency Change (page 125)).
The maximum duration for either active or precharge power-down is limited by the re-
fresh requirements of the device ^tRFC (MAX). The minimum duration for power-down
entry and exit is limited by the ^tCKE (MIN) parameter. The following must be main-
tained while in power-down mode: CKE LOW, a stable clock signal, and stable power
supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t
Care” except ODT. Detailed ODT timing diagrams for different power-down modes are
shown in Figure 83 (page 130)–Figure 88 (page 134).
The power-down state is synchronously exited when CKE is registered HIGH (in con-
junction with a NOP or DESELECT command), as shown in Figure 70 (page 119).
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
118
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