MT46V32M16P-6TF Datasheet, PDF (80/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate SDRAM Features

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 44: WRITE-to-READ – Interrupting
CK#
CK
Command
T0
WRITE
Address
Bank a,
Col b
t_{DQSS (NOM)}
DQS
t_DQSS
T1 T1n T2 T2n T3 T3n T4
NOP
NOP
READ
NOP
t_WTR
Bank a,
Col n
CL = 2
DQ
DI
b
DM
t_{DQSS (MIN)}
DQS
t_DQSS
CL = 2
DQ
DI
b
DM
t_{DQSS (MAX)}
DQS
t_DQSS
DQ
DI
b
DM
CL = 2
T5 T5n T6 T6n
NOP
NOP
DO
n
DO
n
DO
n
Transitioning Data
Don’t Care
Notes:
1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. ^tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ com-
mand will not mask these two data elements.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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