MT46V32M16P-6TF Datasheet, PDF (69/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate SDRAM Features

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 33: READ-to-WRITE
CK#
CK
Command
Address
T0
READ
Bank,
Col n
DQS
DQ
DM
CK#
CK
Command
Address
T0
READ
Bank,
Col n
DQS
DQ
DM
CK#
CK
Command
Address
T0
READ
Bank a,
Col n
DQS
DQ
DM
T1
BST1
CL = 2
T2 T2n T3
T4 T4n T5 T5n
NOP
WRITE
NOP
NOP
Bank,
Col b
tDQ_SS
(NOM)
DO
DI
n
b
T1
T2 T2n T3 T3n T4
T5 T5n
BST1
NOP
NOP
WRITE
NOP
CL = 2.5
Bank,
Col b
tDQ_SS
(NOM)
DO
DI
n
b
T1
T2
BST¹
NOP
CL = 3
T3 T3n T4
T5 T5n
NOP
WRITE
NOP
tDQ_SS
(NOM)
DO
DI
n
b
Transitioning Data
Don’t Care
Notes:
1. Page remains open.
2. DO n = data-out from column n; DI b = data-in from column b.
3. BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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