MT46V32M16P-6TF Datasheet, PDF (10/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate SDRAM Features

512Mb: x4, x8, x16 DDR SDRAM
Pin and Ball Assignments and Descriptions
Table 4: Pin and Ball Descriptions
FBGA
Numbers
K7, L8, L7,
M8, M2, L3,
L2, K3, K2,
J3, K8,
J2, H2
J8, J7
G2, G3
H3
H8
F3
F7, F3
H7, G8,
G7
A8, B9, B7,
C9, C7, D9,
D7, E9, E1,
D3, D1, C3,
C1, B3, B1,
A2
A8, B7, C7,
D7, D3, C3,
B3, A2
B7, D7, D3,
B3
TSOP
Numbers
29, 30, 31,
32, 35, 36,
37, 38, 39,
40, 28
41, 42
26, 27
45, 46
44
24
47
20,47
23, 22,
21
2, 4, 5,
7, 8, 10,
11, 13, 54,
56, 57, 59,
60, 62, 63,
65
2, 5, 8,
11, 56, 59,
62, 65
5, 11, 56,
62
Symbol
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A9, A10,
A11, A12
BA0, BA1
CK, CK#
CKE
CS#
DM
LDM, UDM
RAS#, CAS#,
WE#
DQ[2:0]
DQ[5:3]
DQ[8:6]
DQ[11:9]
DQ[14:12]
DQ15
DQ[2:0]
DQ[5:3]
DQ6, DQ7
DQ[2:0]
DQ3
Type
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE REGISTER command.
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1
also define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER (LMR) command.
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers, and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is
synchronous for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and write
accesses. Input buffers (excluding CK, CK#, and CKE) are disabled during
POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V_DD is applied and until CKE is first brought HIGH, after which it
becomes a SSTL_2 input only.
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems with
multiple banks. CS# is considered part of the command code.
Input data mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data during a
write access. DM is sampled on both edges of DQS. Although DM pins are
input-only, the DM loading is designed to match that of DQ and DQS
pins. For the x16, LDM is DM for DQ[7:0] and UDM is DM for DQ[15:8]. Pin
20 is a NC on x4 and x8.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Data input/output: Data bus for x16.
Data input/output: Data bus for x8.
Data input/output: Data bus for x4.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.