N2M400FDB311A3CE Datasheet, PDF (8/19 Pages) Micron Technology – e·MMC™ Memory

Micron Confidential and Proprietary
Preliminary
Architecture
Figure 5: e·MMC Functional Block Diagram
e·MMC
4GB, 8GB, 16GB, 32GB: e·MMC
Architecture
RST_n
CMD
CLK
V_DDI
MMC
controller
Registers
OCR CSD RCA
CID ECSD DSR
V_CC
V_CCQ
DAT[7:0]
V_SS1
V_SSQ1
NAND Flash
Note: 1. V_SS and V_SSQ are internally connected.
MMC Protocol Independent of NAND Flash Technology
The MMC specification defines the communication protocol between a host and a de-
vice. The protocol is independent of the NAND Flash features included in the device.
The device has an intelligent on-board controller that manages the MMC communica-
tion protocol.
The controller also handles block management functions such as logical block alloca-
tion and wear leveling. These management functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
The device handles these management functions internally, making them invisible to
the host processor.
Defect and Error Management
Micron e·MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
space allocated for the user.
The device also includes a built-in error correction code (ECC) algorithm to ensure that
data integrity is maintained.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.
PDF: 09005aef84a4d6f1
emmc_4gb_8gb_16gb_32gb_100b-it.pdf - Rev. C 7/12 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.