MT46V32M16P-5BJ Datasheet, PDF (75/93 Pages) Micron Technology – Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks

512Mb: x4, x8, x16 DDR SDRAM
Operations
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 40 on page 77 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 41 on page 78. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 42 on page 78.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, ^tWTR should be met, as shown in Figure 43
on page 79.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 44 on page 80.
Note that only the data-in pairs that are registered prior to the ^tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 45 on page 81.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, ^tWR should be met, as shown in
Figure 46 on page 82.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 47 on page 83 and Figure 48 on page 84. Only the data-in pairs regis-
tered prior to the ^tWR period are written to the internal array; any subsequent data-in
should be masked with DM, as shown in Figures 47 and 48. After the PRECHARGE
command, a subsequent command to the same bank cannot be issued until ^tRP is met.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN
75
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