MT46V32M16P-5BJ Datasheet, PDF (72/93 Pages) Micron Technology – Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 36: x4, x8 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window
T1
CK#
CK
tHP1
T2
T2n
T3
T3n
T4
tHP1
tDQ_SQ2
tHP1
tHP1
tDQ_SQ2
tHP1
tDQ_SQ2
tHP1
tDQ_SQ2
DQS³
DQ (last data valid)
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)
tQH5
tQH5
tQH5
tQH5
DQ (last data valid)
DQ (first data no longer valid)
T2
T2n
T3
T3n
T2
T2n
T3
T3n
All DQ and DQS collectively⁶
T2
T2n
T3
T3n
Earliest signal transition
Notes:
Latest signal transition
Data
valid
window
Data
valid
window
Data
valid
window
Data
valid
window
1. ^tHP is the lesser of ^tCL or ^tCH clock transition collectively when a bank is active.
2. ^tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends with the last valid DQ transition.
3. DQ transitioning after DQS transition define the ^tDQSQ window. DQS transitions at T2 and
T2n are an “early DQS”; at T3, a “nominal DQS”; and at T3n, a “late DQS”.
4. For a x4, only two DQ apply.
5. ^tQH is derived from ^tHP: ^tQH = ^tHP - ^tQHS.
6. The data valid window is derived for each DQS transitions and is defined as ^tQH - ^tDQSQ.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN
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