MT46V32M16P-5BJ Datasheet, PDF (47/93 Pages) Micron Technology – Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks

512Mb: x4, x8, x16 DDR SDRAM
Commands
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when ^tRFC
is met. Once ^tRFC is met, the DDR SDRAM will be in the all banks idle state.
• Accessing mode register: Starts with registration of an LMR command and ends when
t_{MRD has been met. Once} t_{MRD is met, the DDR SDRAM will be in the all banks idle}
state.
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t_{RP is met. Once} t_{RP is met, all banks will be in the idle state.}
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
Table 33: Truth Table 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table; Notes appear on page 47
Current State
Any
Idle
Row activating, active,
or precharging
Read (auto precharge
disabled)
Write (auto precharge
disabled)
Read (with auto-
precharge)
Write (with auto-
precharge)
CS# RAS# CAS# WE# Command/Action
H
X
X
X DESELECT (NOP/continue previous operation)
L
H
H
H NO OPERATION (NOP/continue previous operation)
X
X
X
X Any command otherwise allowed to bank m
L
L
H
H ACTIVE (select and activate row)
L
H
L
H READ (select column and start READ burst)
L
H
L
L WRITE (select column and start WRITE burst)
L
L
H
L PRECHARGE
L
L
H
H ACTIVE (select and activate row)
L
H
L
H READ (select column and start new READ burst)
L
H
L
L WRITE (select column and start WRITE burst)
L
L
H
L PRECHARGE
L
L
H
H ACTIVE (select and activate row)
L
H
L
H READ (select column and start READ burst)
L
H
L
L WRITE (select column and start new WRITE burst)
L
L
H
L PRECHARGE
L
L
H
H ACTIVE (select and activate row)
L
H
L
H READ (select column and start new READ burst)
L
H
L
L WRITE (select column and start WRITE burst)
L
L
H
L PRECHARGE
L
L
H
H ACTIVE (select and activate row)
L
H
L
H READ (select column and start READ burst)
L
H
L
L WRITE (select column and start new WRITE burst)
L
L
H
L PRECHARGE
Notes
7
7
7
7, 9
7, 8
7
7
7, 9
7
7
Notes: 1. This table applies when CKE_n-1 was HIGH and CKE_n is HIGH (see Table 35 on page 49) and
after ^tXSNR has been met (if the previous state was self refresh).
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN
47
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