MT46V32M16P-5BJ Datasheet, PDF (56/93 Pages) Micron Technology – Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 23: INITIALIZATION Timing Diagram
VDD
VDDQ
VTT¹
VREF
CK#
CK
CKE
Command
DM
Address
A10
BA0, BA1
DQS
DQ
()()
()()
tVTD1
()()
()()
T0
T1
()()
()()
()()
tCH tCL
()()
LVCMOS
LOW level ₍₎₍₎
((
))
()()
((
))
()()
tIS ^tIH
tIS tIH
NOP
tCK
()()
((
))
PRE
()()
((
))
()()
((
))
()()
()()
()()
((
))
()()
All banks ₍₎₍₎
((
))
((
tIS tIH ⁾⁾
((
))
()()
()()
()()
Ta0
()()
()()
Tb0
()()
()()
Tc0
()()
()()
()()
()()
()()
((
((
((
))
))
))
LMR
()()
((
LMR
()()
((
PRE
()()
((
))
))
))
()()
()()
()()
((
((
((
))
))
))
tIS tIH
Code
()()
((
Code3
()()
((
()()
((
))
))
))
tIS tIH
Code
()()
((
))
tIS tIH
Code
()() ^{All banks} ()()
((
((
)) _{tIS tIH} ))
BA0 = 1 ⁽⁾⁽⁾ BA0 = 0 ⁽⁾⁽⁾
()()
BA1 = 0 ₍₍ BA1 = 0 ₍₍
((
))
))
))
Td0
()()
()()
()()
((
))
AR
()()
((
))
()()
((
))
()()
((
))
()()
((
))
()()
()()
Te0
()()
()()
()()
((
))
AR
()()
((
))
()()
((
))
()()
((
))
()()
((
))
()()
()()
()()
High-Z
()()
()()
()()
()()
()()
()()
()()
High-Z
()()
()()
()()
()()
()()
()()
T = 200µs
Power-up: VDD and CK stable
tRP
tMRD
tMRD
Load extended
mode register
Load mode
register5
tRP
tRFC
200 cycles of CK4
tRFC
Indicates A Break in
Time Scale
Tf0
ACT2
RA
RA
BA
Don’t Care
Notes:
1. VTT is not applied directly to the device; however, ^tVTD ≥ 0 to avoid device latch-up. VDDQ,
VTT, and VREF ≤ VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up,
even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is used between
the VTT supply and the input pin. Once initialized, VREF must always be powered within the
specified range.
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ-
ously issued operating parameters must be used.
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR com-
mand at Ta0.
4. ^tMRD is required before any command can be applied (during MRD time only NOPs or
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
5. While programming the operating parameters, reset the DLL with A8 = 1.
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN
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