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MT47H128M16RT-25EIT Datasheet, PDF (73/134 Pages) Micron Technology – 2Gb: x4, x8, x16 DDR2 SDRAM Features
2Gb: x4, x8, x16 DDR2 SDRAM
Commands
Precharge:
Starts with registration of a PRECHARGE command and ends when
tRP is met. After tRP is met, the bank will be in the idle state.
Read with auto Starts with registration of a READ command with auto precharge
precharge
enabled and ends when tRP has been met. After tRP is met, the
enabled:
bank will be in the idle state.
Row activate:
Starts with registration of an ACTIVATE command and ends when
tRCD is met. After tRCD is met, the bank will be in the row active
state.
Write with auto Starts with registration of a WRITE command with auto precharge
precharge
enabled and ends when tRP has been met. After tRP is met, the
enabled:
bank will be in the idle state.
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):
Refresh:
Starts with registration of a REFRESH command and ends when tRFC is
met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle
state.
Accessing
mode
register:
Starts with registration of the LOAD MODE command and ends when
tMRD has been met. After tMRD is met, the DDR2 SDRAM will be in the
all banks idle state.
Precharge
all:
Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
in a valid state for precharging.
10. A WRITE command may be applied after the completion of the READ burst.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
73
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