MT47H128M16RT-25EIT Datasheet, PDF (30/134 Pages) Micron Technology – 2Gb: x4, x8, x16 DDR2 SDRAM Features

2Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – I_DD Parameters
Table 11: DDR2 I_DD Specifications and Conditions (Die Revision C)
Notes 1–7 apply to the entire table
Parameter/Condition
Symbol Configuration -187E -25E/-25
-3
Operating one bank active-precharge cur-
I_DD0
rent: ^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD), ^tRAS = ^tRAS
MIN (I_DD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are switching; Da-
ta bus inputs are switching
x4, x8
x16
85
75
70
100
90
85
Operating one bank active-read-precharge
I_DD1
current: Iout = 0mA; BL = 4, CL = CL (I_DD), AL = 0;
t_{CK =} t_{CK (IDD),} t_{RC =} t_{RC (IDD),} t_{RAS =} t_{RAS MIN}
(I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are
x4, x8
x16
95
85
80
110
105
100
switching; Data pattern is same as I_DD4W
Precharge power-down current: All banks
I_DD2P
x4, x8, x16
12
12
12
idle; ^tCK = ^tCK (I_DD); CKE is LOW; Other control
and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All banks
idle; ^tCK = ^tCK (I_DD); CKE is HIGH, CS# is HIGH;
Other control and address bus inputs are stable;
Data bus inputs are floating
I_DD2Q
x4, x8
x16
35
30
25
50
45
40
Precharge standby current: All banks idle; ^tCK
= ^tCK (I_DD); CKE is HIGH, CS# is HIGH; Other con-
trol and address bus inputs are switching; Data
bus inputs are switching
I_DD2N
x4, x8
x16
40
35
30
55
50
45
Active power-down current: All banks open;
I_DD3Pf
Fast PDN exit
25
25
25
t_{CK =} t_{CK (IDD); CKE is LOW; Other control and}
MR[12] = 0
address bus inputs are stable; Data bus inputs are _{IDD3Ps Slow PDN exit}
14
14
14
floating
MR[12] = 1
Active standby current: All banks open; ^tCK =
t_{CK (IDD),} t_{RAS =} t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD);}
CKE is HIGH, CS# is HIGH between valid com-
mands; Other control and address bus inputs are
switching; Data bus inputs are switching
I_DD3N
x4, x8
x16
60
50
45
60
50
45
Operating burst write current: All banks
open, continuous burst writes; BL = 4, CL = CL
(I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX
(I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, CS# is HIGH be-
tween valid commands; Address bus inputs are
switching; Data bus inputs are switching
I_DD4W
x4, x8
x16
160
130
110
210
190
170
Operating burst read current: All banks open,
continuous burst reads, I_OUT = 0mA; BL = 4, CL =
CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX
(I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, CS# is HIGH be-
tween valid commands; Address bus inputs are
switching; Data bus inputs are switching
I_DD4R
x4, x8
x16
160
130
110
210
190
170
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
30
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2006 Micron Technology, Inc. All rights reserved.