MT48LC64M4A2_99 Datasheet, PDF (71/77 Pages) Micron Technology – Synchronous DRAM 256Mb: x4, x8, x16 SDRAM

256Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 51: Single Write – With Auto Precharge
T0
CK
tCKS tCKH
CKE
T1
tCK
tCMS tCMH
COMMAND
ACTIVE
NOP2
T2
tCL
tCH
NOP2
DQM/
DQML, DQMU
A0–A9,
A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
DQ
tRCD
tRAS
tRC
T3
T4
T5
NOP2
WRITE
NOP
tCMS tCMH
COLUMN m3
ENABLE AUTO PRECHARGE
BANK
tDS tDH
DIN m
tWR4
T6
T7
T8
T9
NOP
NOP
ACTIVE
NOP
ROW
ROW
BANK
tRP
DON’T CARE
Notes:
1. For this example, BL = 1.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRE-
CHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
4. WRITE command not allowed (would violate ^tRAS).
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
71
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