MT48LC64M4A2_99 Datasheet, PDF (20/77 Pages) Micron Technology – Synchronous DRAM 256Mb: x4, x8, x16 SDRAM

256Mb: x4, x8, x16 SDRAM
Functional Description
Figure 8:
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start driving after T1 and the data will
be valid by T2, as shown in Figure 8. Table 7 on page 21 indicates the operating frequen-
cies at which each CL setting can be used.
Reserved states cannot be used as unknown operation or incompatibility with future
versions may result.
CAS Latency
T0
T1
T2
T3
CLK
COMMAND
READ
DQ
NOP
tLZ
tAC
CL = 2
NOP
tOH
DOUT
CLK
COMMAND
T0
READ
DQ
T1
T2
NOP
NOP
tLZ
tAC
CL = 3
T3
T4
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
20
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