MT48LC4M32B2B5-6G Datasheet, PDF (67/79 Pages) Micron Technology – 128Mb: x32 SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

128Mb: x32 SDRAM
PRECHARGE Operation
Figure 40: WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
NOP
WRITE - AP
Bank n
NOP
READ - AP
Bank m
NOP
NOP
NOP
Bank n
Internal
States
Bank m
Page active
WRITE with burst of 4
Interrupt burst, write-back Precharge
t _{WR - bank n}
tRP _{- bank n}
Page active
READ with burst of 4
NOP
tRP _{- bank m}
Address
DQ
Bank n,
Col a
D_IN
Bank m,
Col d
D_IN
CL = 3 (bank m)
Note: 1. DQM is LOW.
D_OUT
D_OUT
Don’t Care
Figure 41: WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
Internal
States
Bank m
NOP
WRITE - AP
Bank n
NOP
NOP
Page active
WRITE with burst of 4
Page active
WRITE - AP
Bank m
NOP
NOP
NOP
Interrupt burst, write-back Precharge
tWR _{- bank n}
tRP - bank n
tWR _{- bank m}
WRITE with burst of 4
Write-back
Address
DQ
Bank n,
Col a
Bank m,
Col d
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
D_IN
Note: 1. DQM is LOW.
Don’t Care
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
67
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