MT48LC4M32B2B5-6G Datasheet, PDF (27/79 Pages) Micron Technology – 128Mb: x32 SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

128Mb: x32 SDRAM
Commands
WRITE
The WRITE command is used to initiate a burst write access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the write
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Input data appearing on the DQ is written to the memory array, subject to the DQM in-
put logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data is written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that
byte/column location.
Figure 10: WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
A10¹
BA0, BA1
Column address
EN AP
DIS AP
Bank address
Valid address
Don’t Care
Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
27
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