MT48LC4M32B2B5-6G Datasheet, PDF (54/79 Pages) Micron Technology – 128Mb: x32 SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

Figure 27: Random WRITE Cycles
T0
T1
T2
T3
CLK
128Mb: x32 SDRAM
WRITE Operation
Command
WRITE
WRITE
WRITE
WRITE
Address
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
DQ
D_IN
D_IN
D_IN
D_IN
Transitioning data
Don’t Care
Note: 1. Each WRITE command can be issued to any bank. DQM is LOW.
Figure 28: WRITE-to-READ
T0
T1
T2
T3
T4
T5
CLK
Command
WRITE
NOP
READ
NOP
NOP
NOP
Address
Bank,
Col n
Bank,
Col b
DQ
D_IN
D_IN
D_OUT
D_OUT
Transitioning data
Don’t Care
Note: 1. The WRITE command can be issued to any bank, and the READ command can be to any
bank. DQM is LOW. CL = 2 for illustration.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
54
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