MT40A2G4PM-083E Datasheet, PDF (63/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 5
Mode Register 5
Mode register 5 (MR5) controls various device operating modes as shown in the follow-
ing register definition table. Not all settings listed may be available on a die; only set-
tings required for speed bin support are available. MR5 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The map-
ping of address pins during the MRS command is shown in the following MR5 Register
Definition table.
Table 19: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode 21 20 19 18 17 – – – 13 12 11 10 9 8 7 6 5 4 3 2 1 0
register
Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 20: MR5 Register Definition
Mode
Register
21
20:18
17
13
12
11
10
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
Data bus inversion (DBI) – READ DBI enable
0 = Disabled
1 = Enabled
Data bus inversion (DBI) – WRITE DBI enable
0 = Disabled
1 = Enabled
Data mask (DM)
0 = Disabled
1 = Enabled
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
63
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