MT40A2G4PM-083E Datasheet, PDF (54/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 2
Table 14: MR2 Register Definition (Continued)
Mode
Register Description
11:9
Dynamic ODT (R_TT(WR)) – Data bus termination setting during WRITEs
000 = R_TT(WR) disabled (WRITE does not affect R_TT value)
001 = RZQ/2 (120 ohm)
010 = RZQ/1 (240 ohm)
011 = High-Z
100 = RZQ/3 (80 ohm)
101 = Reserved
110 = Reserved
111 = Reserved
7:6 Low-power auto self refresh (LPASR) – Mode summary
00 = Manual mode - Normal operating temperature range (T_C: 0°C–85°C)
01 = Manual mode - Reduced operating temperature range (T_C: 0°C–45°C)
10 = Manual mode - Extended operating temperature range (T_C: 0°C–95°C)
11 = ASR mode - Automatically switching among all modes
5:3 CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
1^tCK WRITE preamble
000 = 9 (DDR4-1600)¹
001 = 10 (DDR4-1866)
010 = 11 (DDR4-2133/1600)¹
011 = 12 (DDR4-2400/1866)
100 = 14 (DDR4-2666/2133)
101 = 16 (DDR4-2933,3200/2400)
110 = 18 (DDR4-2666)
111 = 20 (DDR4-2933, 3200)
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
2^tCK WRITE preamble
000 = N/A
001 = N/A
010 = N/A
011 = N/A
100 = 14 (DDR4-2400)
101 = 16 (DDR4-2666/2400)
110 = 18 (DDR4-2933, 3200/2666)
111 = 20 (DDR4-2933, 3200)
8, 2 RFU
0 = Must be programmed to 0
1 = Reserved
1:0 RFU
0 = Must be programmed to 0
1 = Reserved
Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
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