MT40A2G4PM-083E Datasheet, PDF (334/373 Pages) Micron Technology – Programmable data strobe preambles

8Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
3. Applicable for MR2 settings A7 = 1 and A7 = 0; manual mode with extended tempera-
ture range of operation (0–95°C).
4. Applicable for MR2 settings A7 = 0 and A7 = 1; manual mode with reduced temperature
range of operation (0–45°C).
5. I_DD6R and I_DD6A values are typical.
6. When additive latency is enabled for I_DD0, current changes by approximately 0%.
7. When additive latency is enabled for I_DD1, current changes by approximately +5%(x4/x8),
+4%(x16).
8. When additive latency is enabled for I_DD2N, current changes by approximately +0%.
9. When DLL is disabled for I_DD2N, current changes by approximately –23%.
10. When CAL is enabled for I_DD2N, current changes by approximately –25%.
11. When gear-down is enabled for I_DD2N, current changes by approximately 0%.
12. When CA parity is enabled for I_DD2N, current changes by approximately +7%.
13. When additive latency is enabled for I_DD3N, current changes by approximately +0.6%.
14. When additive latency is enabled for I_DD4R, current changes by approximately +5%.
15. When read DBI is enabled for I_DD4R, current changes by approximately 0%.
16. When additive latency is enabled for I_DD4W, current changes by approximately +3%(x4/
x8), +4%(x16).
17. When write DBI is enabled for I_DD4W, current changes by approximately 0%.
18. When write CRC is enabled for I_DD4W, current changes by approximately +10%(x4/x8),
+10%(x16).
19. When CA parity is enabled for I_DD4W, current changes by approximately +12% (x8),
+12% (x16).
20. When 2X REF is enabled for I_DD5R, current changes by approximately –14%.
21. When 4X REF is enabled for I_DD5R, current changes by approximately –33%.
22. I_PP0 test and limit is applicable for I_DD0 and I_DD1 conditions.
23. I_PP3N test and limit is applicable for all I_DD2x, I_DD3x, I_DD4x and I_DD8 conditions; that is, test-
ing I_PP3N should satisfy the I_PPs for the noted I_DD tests.
24. DDR4-1600 and DDR4-1866 use the same I_DD limits as DDR4-2133.
25. The I_DD values must be derated (increased) when operated outside of the range 0°C ≤ T_C
≤ 85°C:
When T_C < 0°C: I_DD2P0, I_DD2P1, and I_DD3P must be derated by 6%; I_DD4R and I_DD4W must be
derated by 4%; I_DD6, I_DD6ET, and I_DD7 must be derated by 11%.
When T_C > 85°C: I_DD0, I_DD1, I_DD2N, I_DD2NT, I_DD2Q, I_DD3N, I_DD3P, I_DD4R, I_DD4W, and I_DD5R must
be derated by 3%; I_DD2Px must be derated by 40%.
26. I_PP6x is applicable to I_DD6N, I_DD6E, I_DD6R and I_DD6A conditions.
Table 150: I_DD, I_PP, and I_DDQ Current Limits; Die Rev. E, G, H
Symbol
Width
I_DD0: One bank ACTIVATE-to- x4
PRECHARGE current
x8
x16
I_PP0: One bank ACTIVATE-to- x4, x8
PRECHARGE I_PP current
x16
I_DD1: One bank ACTIVATE-to- x4
READto- PRECHARGE current _x8
x16
DDR4-2133
40
45
75
3
4
52
57
95
DDR4-2400
43
48
80
3
4
55
60
100
DDR4-2666
46
51
85
3
4
58
63
105
DDR4-2933
49
54
90
3
4
61
66
110
DDR4-3200
52
57
95
3
4
64
69
115
Unit
mA
mA
mA
mA
mA
mA
mA
mA
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
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