N25Q256A13EF840F Datasheet, PDF (61/90 Pages) Micron Technology – Micron Serial NOR Flash Memory

3V, 256Mb: Multiple I/O Serial Flash Memory
ERASE Operations
Figure 33: BULK ERASE Command
Extended
C
DQ0
Dual
C
DQ0[1:0]
Quad
C
DQ0[3:0]
0
7
LSB
Command
MSB
0
3
LSB
Command
MSB
0
1
MSB
LSB
Command
PROGRAM/ERASE SUSPEND Command
To initiate the PROGRAM/ERASE SUSPEND command, S# is driven LOW. The com-
mand code is input on DQ0. The operation is terminated by the PROGRAM/ERASE RE-
SUME command.
PROGRAM/ERASE SUSPEND command enables the memory controller to interrupt
and suspend an array PROGRAM or ERASE operation within the program/erase latency.
If a SUSPEND command is issued during a PROGRAM operation, then the flag status
register bit 2 is set to 1. After erase/program latency time, the flag status register bit 7 is
also set to 1, showing the device to be in a suspended state, waiting for any operation
(see the Operations Allowed/Disallowed During Device States table).
If a SUSPEND command is issued during an ERASE operation, then the flag status regis-
ter bit 6 is set to 1. After erase/program latency time, the flag status register bit 7 is also
set to 1, showing that device to be in a suspended state, waiting for any operation (see
the Operations Allowed/Disallowed During Device States table).
If the time remaining to complete the operation is less than the suspend latency, the de-
vice completes the operation and clears the flag status register bits 2 or 6, as applicable.
Because the suspend state is volatile, if there is a power cycle, the suspend state infor-
mation is lost and the flag status register powers up as 80h.
During an ERASE SUSPEND operation, a PROGRAM or READ operation is possible in
any sector except the one in a suspended state. Reading from a sector that is in a sus-
pended state will output indeterminate data. The device ignores a PROGRAM com-
mand to a sector that is in an ERASE SUSPEND state; it also sets to 1 the flag status reg-
ister bit 4: program failure/protection error, and leaves the write enable latch bit un-
changed. The WRITE LOCK REGISTER, WRITE VOLATILE CONFIGURATION REGIS-
TER, and WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands are
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