N25Q256A13EF840F Datasheet, PDF (42/90 Pages) Micron Technology – Micron Serial NOR Flash Memory

3V, 256Mb: Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
Table 24: Parameter ID (Continued)
Compliant with JEDEC standard JC-42.4 1775.03
Description
Number of dummy clock cycles required before valid output from
DUAL INPUT/OUTPUT FAST READ operation
Number of XIP confirmation bits for DUAL INPUT/OUTPUT FAST
READ
Command code for DUAL INPUT/OUTPUT FAST READ operation
Supports FAST READ operation in dual SPI protocol
Reserved
Supports FAST READ operation in quad SPI protocol
Reserved
Reserved
Reserved
Number of dummy clock cycles required before valid output from
FAST READ operation in dual SPI protocol
Number of XIP confirmation bits for FAST READ operation in dual SPI
protocol
Command code for FAST READ operation in dual SPI protocol
Reserved
Number of dummy clock cycles required before valid output from
FAST READ operation in quad SPI protocol
Number of XIP confirmation bits for FAST READ operation in quad
SPI protocol
Command code for FAST READ operation in quad SPI protocol
Sector type 1 size (4k)
Sector type 1 command code (4k)
Sector type 2 size (64KB)
Sector type 2 command code 64KB)
Sector type 3 size (not present)
Sector type 3 size (not present)
Sector type 4 size (not present)
Sector type 4 size (not present)
Address
(Byte Mode)
3Eh
3Fh
40h
41h–43h
44h–45h
46h
46h
47h
48h–49h
4Ah
4Bh
4Ch
4Ch
4Eh
4Fh
50h
51h
52h
53h
Address (Bit)
20:16
23:21
31:24
0
3:1
4
7:5
–
–
4:0
7:5
7:0
–
4:0
7:5
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Data
00111b
001b
BBh
1
111b
1
111b
FFFFFFh
FFFFh
00111b
001b
BBh
FFFFh
01001b
001b
EBh
0Ch
0Ch
10h
D8h
00h
00h
00h
00h
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. O 12/12 EN
42
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