N25Q256A13EF840F Datasheet, PDF (41/90 Pages) Micron Technology – Micron Serial NOR Flash Memory

3V, 256Mb: Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
Table 24: Parameter ID
Compliant with JEDEC standard JC-42.4 1775.03
Description
Minimum block/sector erase sizes
Address
(Byte Mode)
30h
Write granularity
WRITE ENABLE command required for writing to volatile status reg-
isters
Reserved
4KB erase command code
Supports DUAL OUTPUT FAST READ operation (single input address,
dual output)
Number of address bytes used (3-byte or 4-byte) for array READ,
WRITE, and ERASE commands
Supports double transfer rate clocking
Supports DUAL INPUT/OUTPUT FAST READ operation (dual input ad-
dress, dual output)
Supports QUAD INPUT/OUTPUT FAST READ operation (quad input
address, quad output)
Supports QUAD OUTPUT FAST READ operation (single input address,
quad output)
Reserved
Reserved
Flash size (bits)
Number of dummy clock cycles required before valid output from
QUAD INPUT/OUTPUT FAST READ operation
Number of XIP confirmation bits for QUAD INPUT/OUTPUT FAST
READ operation
Command code for QUAD INPUT/OUTPUT FAST READ operation
Number of dummy clock cycles required before valid output from
QUAD OUTPUT FAST READ operation
Number of XIP confirmation bits for QUAD OUTPUT FAST READ op-
eration
Command code for QUAD OUTPUT FAST READ operation
Number of dummy clock cycles required before valid output from
DUAL OUTPUT FAST READ operation
Number of XIP confirmation bits for DUAL OUTPUT FAST READ oper-
ation
Command code for DUAL OUTPUT FAST READ operation
31h
32h
33h
34h–37h
38h
39h
3Ah
3Bh
3Ch
3Dh
Address (Bit)
0
1
2
3
4
5
6
7
15:8
16
17
18
19
20
21
22
23
31:24
31:0
4:00
7:5
15:8
20:16
23:21
31:24
4:0
7:5
15:8
Data
10
1
0
1
1
1
20h
1
1
1
1
1
1
1
FFh
0FFFFFFFh
01001b
001b
EBh
00111b
001b
6Bh
01000b
000b
3Bh
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. O 12/12 EN
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