MT46V2M32V1 Datasheet, PDF (61/65 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

BANK READ – WITH AUTO PRECHARGE
64Mb: x32
DDR SDRAM
CK#
CK
CKE
COMMAND⁴
T0
t_IS t_IH
t_IS t_IH
NOP5
A0-A7
A9, A10
A8
BA0, BA1
DM
T1
T2
T3
T4
t_CK
t_CH t_CL
ACT
t_IS t_IH
RA
NOP5
RA
RA
IS IH
Bank x
t_RCD
t_RAS6
t_RC
READ2,6
Col n
NOP5
3
t_IS t_IH
Bank x
CL = 2
T5 T5n T6 T6n T7
NOP5
NOP5
NOP5
t_RP
T8
ACT
RA
RA
RA
Bank x
Case 1: ^tAC(MIN) and ^tDQSCK(MIN)
DQS
t_RPRE
t_DQSCK(MIN)
t_RPST
DQ¹
Case 2: ^tAC(MAX) and ^tDQSC(MAX)
DQS
DQ¹
t_LZ(MIN)
t_LZ(MIN)
DO
n
t_AC(MIN)
t_HZ(MIN)
t_DQSCK(MAX)
t_RPRE
t_RPST
t_LZ(MAX)
t_LZ(MAX)
DO
n
t_AC(MAX)
t_HZ(MAX)
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if ^tRAS(MIN) is met by T5.
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.