MT46V2M32V1 Datasheet, PDF (32/65 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

CK#
CK
COMMAND
T0
WRITE
T1 T1n T2 T2n T3
NOP
NOP
NOP
ADDRESS
Bank a,
Col b
t_{DQSS (NOM)}
DQS
t_DQSS
DQ
DI
b
DM
t_{DQSS (MIN)}
DQS
DQ
DM
t_DQSS
DI
b
t_{DQSS (MAX)}
DQS
t_DQSS
DQ
DI
b
DM
T4
NOP
t_WR
64Mb: x32
DDR SDRAM
T5
T6
PRE⁷
Bank,
(a or all)
NOP
t_RP
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. ^tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE and WRITE commands may
be to different devices, in which case ^tWR is not required and the PRECHARGE command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
Figure 22
WRITE to PRECHARGE – Uninterrupting
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
32
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©2001, Micron Technology, Inc.