MT46V2M32V1 Datasheet, PDF (1/65 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

DOUBLE DATA RATE
(DDR) SDRAM
64Mb: x32
DDR SDRAM
MT46V2M32V1- 512K x 32 x 4 banks
MT46V2M32 - 512K x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
FEATURES
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Reduced output drive option
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh (7.8µs/cycle)
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Programmable I/O (SSTL_2 compatible) – reduced
and impedance matched
OPTIONS
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Power Supply
2.5V VDD/VDDQ
2.65V VDD/VDDQ
• Plastic Package
100-pin TQFP (0.65mm lead pitch)
• Timing - Cycle Time
200 MHz @ CL = 3
183 MHz @ CL = 3
166 MHz @ CL = 3
150 MHz @ CL = 3
MARKING
2M32
V1
none
LG
-5
-55
-6
-65
Part Number Example:
MT46V2M32V1LG-5
64Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V2M32LG
ARCHITECTURE
2 Meg x 32
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
(Normal Bend Shown)
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
VREF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
GRADE
-5
-55
-6
-65
CLOCK RATE
CL = 2**
CL = 3**
125 MHz
100 MHz
100 MHz
100 MHz
200 MHz
183 MHz
166 MHz
150 MHz
DATA-OUT ACCESS DQS-DQ
WINDOW* WINDOW SKEW
1.5ns
1.8ns
1.9ns
2.1ns
±0.75ns
±0.75ns
±0.75ns
±0.75ns
+0.5ns
+0.5ns
+0.5ns
+0.5ns
*Minimum clock rate @ CL = 3
**CL = CAS (Read) Latency
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.