MT46V2M32V1 Datasheet, PDF (19/65 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

CK#
CK
COMMAND
T0
READ
T1
READ
64Mb: x32
DDR SDRAM
T2 T2n T3 T3n T4 T4n T5 T5n
READ
READ
NOP
NOP
ADDRESS
Bank,
Col n
DQS
DQ
CK#
CK
COMMAND
T0
READ
Bank,
Col x
CL = 2
T1
READ
Bank,
Col b
Bank,
Col g
DO
DO
DO
DO
DO
DO
DO
n
n'
x
x'
b
b'
g
T2
T3 T3n T4 T4n T5 T5n
READ
READ
NOP
NOP
ADDRESS
Bank,
Col n
DQS
Bank,
Col x
CL = 3
Bank,
Col b
Bank,
Col g
DQ
DO
DO
DO
DO
DO DO
n
n'
x
x'
b
b'
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).
3. n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
Figure 10
Random READ Accesses
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
19
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©2001, Micron Technology, Inc.