MT48LC2M32B2TG-7ITG Datasheet, PDF(60/80 Page) Micron Technology – SDR SDRAM MT48LC2M32B2

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MT48LC2M32B2TG-7ITG Datasheet, PDF (60/80 Pages) Micron Technology – SDR SDRAM MT48LC2M32B2 – 512K x 32 x 4 Banks

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64Mb: x32 SDRAM

WRITE Operation

Figure 33: WRITE â DQM Operation

CLK

tCK

tCL

tCH

tCKS tCKH

CKE

tCMS tCMH

Command

ACTIVE

NOP

WRITE

NOP

tCMS tCMH

DQM

Address

A10

BA0, BA1

tAS tAH

Row

tAS tAH

Row

tAS tAH

Bank

Column m

Enable auto precharge

Disable auto precharge

Bank

tDS tDH

DIN

tDS tDH

DIN

tDS tDH

DIN

tRCD

Note: 1. For this example, BL = 4.

NOP

Donât Care

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit

(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access

of a single column location (burst of one), regardless of the programmed burst length.

READ commands access columns according to the programmed burst length and se-

quence, just as in the normal mode of operation (M9 = 0).

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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