MT48LC2M32B2TG-7ITG Datasheet, PDF (1/80 Pages) Micron Technology – SDR SDRAM MT48LC2M32B2 – 512K x 32 x 4 Banks

SDR SDRAM
MT48LC2M32B2 – 512K x 32 x 4 Banks
64Mb: x32 SDRAM
Features
Features
• PC100-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 4096-cycle refresh
(commercial and industrial)
– 16ms, 4096-cycle refresh
(automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Options
• Configuration
– 2 Meg x 32 (512K x 32 x 4 banks)
• Plastic package – OCPL¹
– 86-pin TSOP II (400 mil) standard
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm) Pb-
free
• Timing – cycle time
– 5ns (200 MHz)
– 5.5ns (183 MHz)
– 6ns (167 MHz)
– 6ns (167 MHz)
– 7ns (143 MHz)
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
• Revision
Marking
2M32B2
TG
P
B5
-5
-55²
-6A³
-6²
-7²
None
IT
AT⁴
:G/:J
Notes:
1. Off-center parting line.
2. Available only on revision G.
3. Available only on revision J.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Clock
Speed Grade
Frequency (MHz)
-5
200
-55
183
-6A
167
-6
167
-7
143
Target ^tRCD-^tRP-CL
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
t_{RCD (ns)}
15
16.5
18
18
20
t_{RP (ns)}
15
16.5
18
18
20
CL (ns)
15
16.5
18
18
21
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.