MT48LC2M32B2TG-7ITG Datasheet, PDF (20/80 Pages) Micron Technology – SDR SDRAM MT48LC2M32B2 – 512K x 32 x 4 Banks

64Mb: x32 SDRAM
Electrical Specifications – I_DD Parameters
Table 11: I_DD Specifications and Conditions – Revision J
Notes 1–5 apply to all parameters and conditions; V_DD, V_DDQ = 3.3V ±0.3V
Parameter/Condition
Operating current: Active mode; Burst = 2; READ or WRITE; ^tRC ≥ ^tRC (MIN); CL = 3
Standby current: Power-down mode; All banks idle; CKE = LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after ^tRCD
met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active;
CL = 3
Auto refresh current: CL = 3; CKE, CS# = HIGH
t_{RFC =} t_{RFC (MIN)}
Self refresh current: CKE ≤ 0.2V
Symbol
I_DD1
I_DD2
I_DD3
Max
-6A
120
2.5
45
I_DD4
120
I_DD5
180
I_DD6
3
Unit
mA
mA
mA
Notes
6, 7, 8, 9
6, 8, 9, 10
mA 6, 7, 8, 9
mA 6, 7, 8, 9, 10
mA
11
Notes:
1. All voltages referenced to V_SS.
2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (V_DD and V_DDQ must be powered
up simultaneously. V_SS and V_SSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the ^tREF refresh requirement is excee-
ded.
3. AC timing and I_DD tests have V_IL = 0.25V and V_IH = 2.75V, with timing referenced to 1.5V
crossover point.
4. I_DD specifications are tested after the device is properly initialized.
5. V_DD = 3.135V for -6, -55, and -5 speed grades.
6. I_DD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. The I_DD current will decrease as the CL is reduced. This is due to the fact that the maxi-
mum cycle rate is slower as the CL is reduced.
8. Address transitions average one transition every two clocks.
9. ^tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
10. Other input signals are allowed to transition no more than once in any two-clock period
and are otherwise at valid V_IH or V_IL levels.
11. Enables on-chip refresh and address counters.
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
20
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